Cadence announced on April 29 (US time) that it has significantly expanded its design IP portfolio optimized for Intel® 18A and Intel® 18A-P technologies, and has certified Cadence® digital and analog/custom design solutions for the latest Intel® 18A process design kit (PDK). Through its strategic partnership with Intel Foundry, Cadence continues to drive innovation and leadership in artificial intelligence and machine learning (AI/ML), high performance computing (HPC), and advanced mobility applications.
Cadence has worked closely with Intel Foundry to design and optimize comprehensive solutions that take full advantage of Intel’s 18A/18A-P node innovative features, including RibbonFET GAA (Gate-all-around) transistors and PowerVia BSPDN (Back Side Power Delivery Network), to achieve superior power, performance and area (PPA) efficiency and accelerate time to market for leading-edge SoC designs.
The latest additions to Cadence’s extensive design IP portfolio for Intel 18A/18A-P technology will be available soon:
Universal Accelerator Link™ (UALink™), the latest standard for scaling up and scaling out accelerator networks in AI factories, and long-range 224G SerDes for Ultra Ethernet™
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DDR5 – 12.8G with MRDIMM Gen2, supporting the latest DRAM technology for AI applications
Universal Chiplet Interconnect Express™ (UCIe™) 1. 1 48G, seamlessly facilitates integration of multi-die system-in-package (SiP) for high data rate, scalable chiplet architectures
Advanced computing and peripheral connectivity IP compatible with the latest consumer standards enables scalable embedded applications that address a wide range of consumer and mobility requirements:
10G multi-protocol SerDes PHY, supporting PCI Express® (PCIe®) 3.0, DisplayPort and Ethernet
eUSB2 v2.0
MIPI®SoundWire®I3S
Cadence’s expanded portfolio also includes design IP already available for the Intel 18A technology family:
112G Extended Long-Reach SerDes, PCIe 6.0, CXL 3.0 with superior Bit Error Rate (BER) performance for robust data integrity over long distances
64G MP PHY for 56G Ethernet, Multi-Standard LPDDR5X/5 – 8533 Mbps
UCIe 1.0 16G for Advanced Packaging
This gives customers a broader range of IP options for AI/ML, HPC and mobility applications leveraging Intel® 18A/18A-P RibbonFET and PowerVia implementations.
In addition to the new IP for Intel 18A and 18A-P technologies, Cadence’s comprehensive AI-driven suite has been certified on the latest Intel 18A node PDK, including the Cadence RTL-to-GDS flow, a robust AI-driven solution that includes the Cadence Cerebrus® Intelligent Chip Explorer, Genus™ Synthesis Solution, Innovus™ Implementation System, Quantus™ Extraction Solution, Quantus Field Solver, Tempus™ Timing Solution and Pegasus™ Verification System, as well as custom IC design solutions such as Cadence Virtuoso® Studio, the unified Spectre® platform and the Voltus™-XFi Custom Power Integrity solution.
Meanwhile, Cadence and Intel Foundry are working to co-optimize early design technologies for Intel 14A-E to prepare Cadence EDA flows for next-generation advanced nodes.
Additionally, Cadence and Intel Foundry are partnering to develop advanced packaging workflows leveraging EMIB-T (Embedded Multi-die Interconnect Bridge-T) technology . This solution streamlines the integration of complex multi-chiplet architectures, eliminates data translation, shortens design cycles, and enables parallel work with early thermal, signal integrity and power modeling. It also simplifies the adoption of Intel technologies by ensuring standards compliance and reducing risk.
Cadence continues to support the Intel Foundry Accelerator Alliance Program and has joined the Intel Foundry Chiplet Alliance Program as a founding member to ensure that Cadence solutions provide a reliable, scalable path for customers to deploy designs leveraging interoperable, secure chiplet solutions for targeted applications and markets. Cadence already participates in the EDA, IP, Design Services and USMAG Alliances.
SOURCE: PRTimes
