Cadence Design Systems, Inc. announced a new, multi-year partnership with Samsung Foundry. This collaboration will speed up the creation of advanced SoCs, 3D-ICs, and chiplets. These technologies will focus on AI data centers, automotive systems, and next-generation connectivity. This partnership brings together Cadence’s AI design tools and Samsung’s advanced process nodes. These include SF4X, SF5A, SF2P, and SF4U. Together, they create high-performance, low-power semiconductor solutions.
Enhanced IP Portfolio for Next-Gen Applications
As part of the extended agreement, Cadence will broaden its portfolio of memory and interface IP solutions optimized for Samsung’s advanced nodes. These include:
- LPDDR6/5X-14.4G, GDDR7-36G, DDR5-9600
- PCIe® 6.0/5.0/CXL 3.2, UCIe™-SP 32G
- 10G multi-protocol PHY (supporting USB3.x, DP-TX, PCIe 3.0, and SGMII)
- Companion controller IP for complete subsystem solutions
Additionally, new IP such as LPDDR5X-8533 PHY for automotive on SF5A and 32G PCIe 5.0 PHY for SF2P are being introduced to support demanding AI and HPC workloads.
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Advancing Digital Design with Full-Flow Qualification
Cadence’s full digital flow has been successfully validated on Samsung’s SF2P process using the Samsung Hyper Cell methodology. The flow also integrates support for Samsung’s Local Layout Effect (LLE) timing, enhancing accuracy in advanced designs. The two companies continue to collaborate under the Design and Technology Co-Optimization (DTCO) initiative to support upcoming nodes.
The Cadence Pegasus™ Verification System has been certified for SF2P and additional Samsung nodes, ensuring scalable physical verification for large, complex designs while meeting strict accuracy and runtime goals.
Automated Analog IP Migration to 2nm
Cadence and Samsung have automated the migration of 4nm analog cell-based IP to the 2nm process, preserving design integrity while significantly reducing turnaround time. This achievement underscores the value of scalable IP reuse in accelerating next-generation design cycles and reducing development costs.
RF Co-Design for mmWave Applications
The companies have also successfully validated a complete front-end module (FEM) and antenna-in-package (AiP) co-design flow for mmWave applications using Samsung’s 14nm FinFET technology. This reference flow streamlines IC/module development from system-level budgeting through to post-layout verification, improving efficiency and reducing TAT.
3D-IC Power Integrity at Scale
Cadence and Samsung Foundry are working together on 3D-IC development. They use Voltus™ InsightAI, Innovus™, and the Integrity™ 3D-IC Platform. These tools help with complete power integrity analysis. Voltus InsightAI achieved 80–90% accuracy in fixing IR drop issues on Samsung’s fast CPU designs at the SF2 node. It optimized power and performance with few trade-offs.
This partnership is a big step for fast innovation in AI, automotive, and connectivity. It’s supported by strong EDA tools, trusted IP, and advanced process technology.
