{"id":16143,"date":"2025-06-18T13:24:07","date_gmt":"2025-06-18T13:24:07","guid":{"rendered":"https:\/\/itbusinesstoday.com\/?p=16143"},"modified":"2025-06-18T13:24:07","modified_gmt":"2025-06-18T13:24:07","slug":"cadence-and-samsung-team-up-to-advance-chip-design","status":"publish","type":"post","link":"https:\/\/itbusinesstoday.com\/ja\/industrial-tech\/semiconductorandelectronics\/cadence-and-samsung-team-up-to-advance-chip-design\/","title":{"rendered":"\u30b1\u30a4\u30c7\u30f3\u30b9\u3068\u30b5\u30e0\u30b9\u30f3\u304c\u30c1\u30c3\u30d7\u8a2d\u8a08\u306e\u9ad8\u5ea6\u5316\u3067\u63d0\u643a"},"content":{"rendered":"<?xml encoding=\"utf-8\" ?><p>Cadence Design Systems, Inc. announced a new, multi-year partnership with Samsung Foundry. This collaboration will speed up the creation of advanced SoCs, 3D-ICs, and chiplets. These technologies will focus on AI data centers, automotive systems, and next-generation connectivity. This partnership brings together Cadence&rsquo;s AI design tools and Samsung&rsquo;s advanced process nodes. These include SF4X, SF5A, SF2P, and SF4U. Together, they create high-performance, low-power semiconductor solutions.<\/p><p><strong>\u6b21\u4e16\u4ee3\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u5411\u3051IP\u30dd\u30fc\u30c8\u30d5\u30a9\u30ea\u30aa\u306e\u5f37\u5316<\/strong><\/p><p>As part of the extended agreement, Cadence will broaden its portfolio of memory and interface IP solutions optimized for Samsung&rsquo;s advanced nodes. These include:<\/p><ul>\n<li>LPDR6\/5X-14.4G\u3001GDR7-36G\u3001DDR5-9600<\/li>\n<li>PCIe&reg; 6.0\/5.0\/CXL 3.2, UCIe&trade;-SP 32G<\/li>\n<li>10G\u30de\u30eb\u30c1\u30d7\u30ed\u30c8\u30b3\u30ebPHY\uff08USB3.x\u3001DP-TX\u3001PCIe 3.0\u3001SGMII\u3092\u30b5\u30dd\u30fc\u30c8\uff09<\/li>\n<li>\u5b8c\u5168\u306a\u30b5\u30d6\u30b7\u30b9\u30c6\u30e0\u30fb\u30bd\u30ea\u30e5\u30fc\u30b7\u30e7\u30f3\u306e\u305f\u3081\u306e\u30b3\u30f3\u30d1\u30cb\u30aa\u30f3\u30fb\u30b3\u30f3\u30c8\u30ed\u30fc\u30e9IP<\/li>\n<\/ul><p>\u3055\u3089\u306b\u3001SF5A\u306e\u8eca\u8f09\u7528LPDDR5X-8533 PHY\u3084SF2P\u306e32G PCIe 5.0 PHY\u306a\u3069\u306e\u65b0\u3057\u3044IP\u3092\u5c0e\u5165\u3057\u3001\u8981\u6c42\u306e\u53b3\u3057\u3044AI\u3084HPC\u30ef\u30fc\u30af\u30ed\u30fc\u30c9\u3092\u30b5\u30dd\u30fc\u30c8\u3057\u307e\u3059\u3002<\/p><h4>\u3053\u3061\u3089\u3082\u304a\u8aad\u307f\u304f\u3060\u3055\u3044\uff1a <a class=\"p-url\" href=\"https:\/\/itbusinesstoday.com\/ja\/industrial-tech\/semiconductorandelectronics\/mitsubishi-electric-corp-ge-bernova-sign-hvdc-chip-mou\/\" rel=\"bookmark\">\u4e09\u83f1\u96fb\u6a5f\u3001GE\u30d9\u30eb\u30ce\u30d0\u3068HVDC\u30c1\u30c3\u30d7\u306b\u95a2\u3059\u308bMoU\u3092\u7de0\u7d50<\/a><\/h4><p><strong>\u30d5\u30eb\u30d5\u30ed\u30fc\u30fb\u30af\u30aa\u30ea\u30d5\u30a3\u30b1\u30fc\u30b7\u30e7\u30f3\u306b\u3088\u308b\u30c7\u30b8\u30bf\u30eb\u8a2d\u8a08\u306e\u9032\u5316<\/strong><\/p><p>Cadence&rsquo;s full digital flow has been successfully validated on Samsung&rsquo;s SF2P process using the Samsung Hyper Cell methodology. The flow also integrates support for Samsung&rsquo;s Local Layout Effect (LLE) timing, enhancing accuracy in advanced designs. The two companies continue to collaborate under the Design and Technology Co-Optimization (DTCO) initiative to support upcoming nodes.<\/p><p>The Cadence Pegasus&trade; Verification System has been certified for SF2P and additional Samsung nodes, ensuring scalable physical verification for large, complex designs while meeting strict accuracy and runtime goals.<\/p><p><strong>\u30a2\u30ca\u30ed\u30b0IP\u306e2nm\u3078\u306e\u81ea\u52d5\u30de\u30a4\u30b0\u30ec\u30fc\u30b7\u30e7\u30f3<\/strong><\/p><p>\u30b1\u30a4\u30c7\u30f3\u30b9\u3068\u30b5\u30e0\u30b9\u30f3\u306f\u30014nm\u30a2\u30ca\u30ed\u30b0\u30fb\u30bb\u30eb\u30fb\u30d9\u30fc\u30b9\u306eIP\u306e2nm\u30d7\u30ed\u30bb\u30b9\u3078\u306e\u79fb\u884c\u3092\u81ea\u52d5\u5316\u3057\u3001\u30c7\u30b6\u30a4\u30f3\u306e\u5b8c\u5168\u6027\u3092\u7dad\u6301\u3057\u306a\u304c\u3089\u30bf\u30fc\u30f3\u30a2\u30e9\u30a6\u30f3\u30c9\u30fb\u30bf\u30a4\u30e0\u3092\u5927\u5e45\u306b\u77ed\u7e2e\u3057\u307e\u3057\u305f\u3002\u3053\u306e\u6210\u679c\u306f\u3001\u6b21\u4e16\u4ee3\u8a2d\u8a08\u30b5\u30a4\u30af\u30eb\u306e\u52a0\u901f\u3068\u958b\u767a\u30b3\u30b9\u30c8\u306e\u524a\u6e1b\u306b\u304a\u3044\u3066\u3001\u30b9\u30b1\u30fc\u30e9\u30d6\u30eb\u306aIP\u518d\u5229\u7528\u306e\u4fa1\u5024\u3092\u5f37\u8abf\u3059\u308b\u3082\u306e\u3067\u3059\u3002<\/p><p><strong>\u30df\u30ea\u6ce2\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u306e\u305f\u3081\u306eRF\u5354\u8abf\u8a2d\u8a08<\/strong><\/p><p>The companies have also successfully validated a complete front-end module (FEM) and antenna-in-package (AiP) co-design flow for mmWave applications using Samsung&rsquo;s 14nm FinFET technology. This reference flow streamlines IC\/module development from system-level budgeting through to post-layout verification, improving efficiency and reducing TAT.<\/p><p><strong>\u30b9\u30b1\u30fc\u30eb\u3067\u306e3D-IC\u30d1\u30ef\u30fc\u30a4\u30f3\u30c6\u30b0\u30ea\u30c6\u30a3<\/strong><\/p><p><a href=\"https:\/\/www.cadence.com\/ja_JP\" data-no-translation=\"\">Cadence&nbsp;<\/a>\u305d\u3057\u3066 <a href=\"https:\/\/www.samsungfoundry.com\/\" data-no-translation=\"\">Samsung Foundry<\/a> are working together on 3D-IC development. They use Voltus&trade; InsightAI, Innovus&trade;, and the Integrity&trade; 3D-IC Platform. These tools help with complete power integrity analysis. Voltus InsightAI achieved 80&ndash;90% accuracy in fixing IR drop issues on Samsung&rsquo;s fast CPU designs at the SF2 node. It optimized power and performance with few trade-offs.<\/p><p>This partnership is a big step for fast innovation in AI, automotive, and connectivity. It&rsquo;s supported by strong EDA tools, trusted IP, and advanced process technology.<\/p>","protected":false},"excerpt":{"rendered":"<p>Cadence Design Systems, Inc. announced a new, multi-year partnership with Samsung Foundry. This collaboration will speed up the creation of advanced SoCs, 3D-ICs, and chiplets. These technologies will focus on AI data centers, automotive systems, and next-generation connectivity. This partnership brings together Cadence&rsquo;s AI design tools and Samsung&rsquo;s advanced process nodes. These include SF4X, SF5A, SF2P, and SF4U. Together, they create high-performance, low-power semiconductor solutions.Enhanced IP Portfolio for Next-Gen ApplicationsAs part of the extended agreement, Cadence will broaden its portfolio of memory and interface IP solutions optimized for Samsung&rsquo;s advanced nodes. These include: LPDDR6\/5X-14.4G, GDDR7-36G, DDR5-9600 PCIe&reg; 6.0\/5.0\/CXL 3.2, UCIe&trade;-SP 32G 10G multi-protocol PHY (supporting USB3.x, DP-TX, PCIe 3.0, and [&hellip;]<\/p>\n","protected":false},"author":7,"featured_media":16176,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"wprm-recipe-roundup-name":"","wprm-recipe-roundup-description":"","postBodyCss":"","postBodyMargin":[],"postBodyPadding":[],"postBodyBackground":{"backgroundType":"classic","gradient":""},"footnotes":""},"categories":[84,207,237,192],"tags":[1595,4146,4142,5465,5466,5467],"ppma_author":[572],"class_list":["post-16143","post","type-post","status-publish","format-standard","has-post-thumbnail","category-industrial-tech","category-international","category-news","category-semiconductorandelectronics","tag-ai-data-center","tag-cadence","tag-eda-tools","tag-ip-solutions","tag-samsung-foundry","tag-semiconductors"],"yoast_head":"<!-- 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